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HM62W16255HC Series
4M High Speed SRAM (256-kword x 16-bit)
ADE-203-1200 (Z) Preliminary Rev. 0.0 Sep. 1, 2000 Description
The HM62W16255HC is a 4-Mbit high speed static RAM organized 256-kword x 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HC is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.
Features
* Single 3.3 V supply: 3.3 V 0.3 V * Access time: 10 ns (max) * Completely static memory No clock or timing strobe required * Equal access and cycle times * Directly TTL compatible All inputs and outputs * Operating current: 145 mA (max) * TTL standby current: 40 mA (max) * CMOS standby current: 5 mA (max) : 1 mA (max) (L-version) * Data retention current: 0.6 mA (max) (L-version) * Data retention voltage: 2.0 V (min) (L-version) * Center VCC and VSS type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specification.
HM62W16255HC Series
Ordering Information
Type No. HM62W16255HCJP-10 HM62W16255HCLJP-10 HM62W16255HCTT-10 HM62W16255HCLTT-10 Access time 10 ns 10 ns 10 ns 10 ns 400-mil 44-pin plastic TSOPII (TTP-44DE) Package 400-mil 44-pin plastic SOJ (CP-44D)
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HM62W16255HC Series
Pin Arrangement
44-pin SOJ
A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44-pin TSOP
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10
(Top View)
(Top View)
Pin Description
Pin name A0 to A17 I/O1 to I/O16 CS OE WE UB LB VCC VSS NC Function Address input Data input/output Chip select Output enable Write enable Upper byte select Lower byte select Power supply Ground No connection
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HM62W16255HC Series
Block Diagram
(LSB) A14 A13 A12 A5 A6 A7 A11 A10 A3 (MSB) A1 I/O1 . . . I/O8 I/O9 . . . I/O16 WE CS LB UB
VCC Row decoder Memory matrix 1024 rows x 32 columns x 8 blocks x 16 bit (4,194,304 bits) VSS
CS Column I/O Input data control Column decoder CS
(LSB) A8 A9 A17 A15 A16 A0 A2 A4 (MSB)
OE
CS
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HM62W16255HC Series
Operation Table
CS H L L L L L L L L L Note: OE x H L L L L x x x x WE x H H H H H L L L L x: H or L LB x x L L H H L L H H UB x x L H L H L H L H Mode Standby Output disable Read VCC current I SB , I SB1 I CC I CC I/O1-I/O8 High-Z High-Z Output Output High-Z High-Z Input Input High-Z High-Z I/O9-I/O16 High-Z High-Z Output High-Z Output High-Z Input High-Z Input High-Z Ref. cycle -- -- Read cycle Read cycle Read cycle -- Write cycle Write cycle Write cycle --
Lower byte read I CC Upper byte read I CC -- Write I CC I CC
Lower byte write I CC Upper byte write I CC -- I CC
Absolute Maximum Ratings
Parameter Supply voltage relative to VSS Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value -0.5 to +4.6 -0.5* to V CC + 0.5* 1.0 0 to +70 -55 to +125 -10 to +85
1 2
Unit V V W C C C
Notes: 1. VT (min) = -2.0 V for pulse width (under shoot) 6 ns 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns
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HM62W16255HC Series
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC* VSS * Input voltage VIH VIL Notes: 1. 2. 3. 4.
3 4
Min 3.0 0 2.0 -0.5*
1
Typ 3.3 0 -- --
Max 3.6 0 VCC + 0.5* 0.8
2
Unit V V V V
VIL (min) = -2.0 V for pulse width (under shoot) 6 ns VIH (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns The supply voltage with all V CC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
Parameter Input leakage current Output leakage current Operating power supply current Symbol Min |ILI| |ILO | I CC -- -- -- Typ*1 -- -- -- Max 2 2 145 Unit Test conditions A A mA Vin = VSS to V CC Vin = VSS to V CC Min cycle CS = VIL, Iout = 0 mA Other inputs = VIH/VIL Min cycle, CS = VIH, Other inputs = VIH/VIL f = 0 MHz VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V
Standby power supply current
I SB I SB1
-- --
-- TBD
40 5
mA mA
--* 2 Output voltage VOL VOH -- 2.4
TBD*2 -- --
1.0*2 0.4 -- V V I OL = 8 mA I OH = -4 mA
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25C and not guaranteed. 2. This characteristics is guaranteed only for L-version.
6
HM62W16255HC Series
Capacitance (Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance*
1 1
Symbol Cin CI/O
Min -- --
Typ -- --
Max 6 8
Unit pF pF
Test conditions Vin = 0 V VI/O = 0 V
Input/output capacitance* Note:
1. This parameter is sampled and not 100% tested.
7
HM62W16255HC Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: 3.0 V/0.0 V Input rise and fall time: 3 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope and jig)
1.5 V 3.3 V 319 Dout 30 pF 353 5 pF
Dout Zo=50 RL=50
Output load (A)
Output load (B) (for tCLZ, tOLZ, tLBLZ, tUBLZ, tCHZ, tOHZ, tLBHZ, tUBHZ, tWHZ, and tOW)
Read Cycle
HM62W16255HC -10 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Byte select to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Byte select to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Byte deselect to output in high-Z Symbol t RC t AA t ACS t OE t LB, t UB t OH t CLZ t OLZ t LBLZ, t UBLZ t CHZ t OHZ t LBHZ, t UBHZ Min 10 -- -- -- -- 3 3 0 0 -- -- -- Max -- 10 10 5 5 -- -- -- -- 5 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 Notes
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HM62W16255HC Series
Write Cycle
HM62W16255HC -10 Parameter Write cycle time Address valid to end of write Chip select to end of write Write pulse width Byte select to end of write Address setup time Write recovery time Data to write time overlap Data hold from write time Write disable to output in low-Z Output disable to output in high-Z Write enable to output in high-Z Symbol t WC t AW t CW t WP t LBW, t UBW t AS t WR t DW t DH t OW t OHZ t WHZ Min 10 7 7 7 7 0 0 5 0 3 -- -- Max -- -- -- -- -- -- -- -- -- -- 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 8 7 9, 10 5 6 Notes
Notes: 1. Transition is measured 200 mV from steady voltage with Load (B). This parameter is sampled and not 100% tested. 2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state. 3. WE and/or CS must be high during address transition time. 4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. t AS is measured from the latest address transition to the latest of CS, WE, LB or UB going low. 6. t WR is measured from the earliest of CS, WE, LB or UB going high to the first address transition. 7. A write occurs during the overlap of low CS, low WE and low LB or low UB. 8. t CW is measured from the later of CS going low to the end of write. 9. t LBW is measured from the later of LB going low to the end of write. 10. t UBW is measured from the later of UB going low to the end of write.
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HM62W16255HC Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
t RC Address tAA tACS CS tOE OE tLB LB tLBHZ 1 * tOHZ *1 tCHZ *1 Valid address
tUB UB tLBLZ *1 Dout (Lower byte) High Impedance *4 tUBLZ *1 tOLZ *1 tCLZ *1 High Impedance *4 Valid data
tUBHZ1 * *4 tOH
Dout (Upper byte)
Valid data
*4
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HM62W16255HC Series
Read Timing Waveform (2) (WE = VIH, LB = VIL , UB, = VIL)
tRC
Address
Valid address tAA tACS tOH tCHZ*1
CS tOE OE tOLZ*1 tCLZ *1 Dout (Lower/Upper byte) High Impedance *4 Valid data *4 tOHZ*1
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HM62W16255HC Series
Write Timing Waveform (1) (LB, UB Controlled)
tWC Address tAW tAS tWP WE*3 tCW CS*3 Valid address tWR
OE tLBW LB tUBW UB tWHZ tOHZ High impedance tOLZ tOW
Dout (Lower byte)
Dout (Upper byte)
High impedance tDW tDH Valid data tDW tDH Valid data
Din (Lower byte)
Din (Upper byte)
12
HM62W16255HC Series
Write Timing Waveform (2) (WE Controlled)
tWC Address tAW tAS WE*3 tCW CS*3 tWP Valid address tWR
OE tLBW LB, UB tWHZ tOHZ Dout (Lower/Upper byte) High impedance *2 tOLZ tOW tUBW
tDW
tDH Valid data
Din (Lower/Upper byte)
13
HM62W16255HC Series
Write Timing Waveform (3) (CS Controlled)
tWC Address Valid address tAW tAS tWP tWR
WE *3 tCW CS *3
OE tLBW LB, UB tWHZ tOHZ Dout (Lower/Upper byte) High impedance * *2
4
tUBW
tOLZ tOW
tDW
tDH Valid data
Din (Lower/Upper byte)
14
HM62W16255HC Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
This characteristics is guaranteed only for L-version.
Parameter VCC for data retention Symbol VDR Min 2.0 Typ*1 Max -- -- Unit V Test conditions VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V VCC = 3 V VCC CS VCC - 0.2 V, (1) 0 V Vin 0.2 V or (2) VCC Vin VCC - 0.2 V See retention waveform
Data retention current
I CCDR
--
TBD
600
A
Chip deselect to data retention time Operation recovery time Note:
t CDR tR
0 5
-- --
-- --
ns ms
1. Typical values are at VCC = 3.0 V, Ta = +25C, and not guaranteed.
Low V CC Data Retention Timing Waveform
t CDR V CC 3.0 V Data retention mode tR
V DR 2.0 V CS 0V VCC CS VCC - 0.2 V
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HM62W16255HC Series
Package Dimensions
HM62W16255HCJP/HCLJP Series (CP-44D)
Unit: mm
28.33 28.90 Max 44 23 10.16 0.13 0.74 1.30 Max 3.50 0.26 1 22 11.18 0.13
0.80 +0.25 -0.17
*0.43 0.10 0.41 0.08
1.27
9.40 0.25
0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Mass (reference value)
CP-44D Conforms -- 1.8 g
16
2.65 0.12
HM62W16255HC Series
HM62W16255HCTT/HCLTT Series (TTP-44DE)
Unit: mm
18.41 18.81 Max 44 23
1 *0.27 0.07 0.25 0.05
0.80 0.13 M
22 0.80
10.16
1.005 Max *0.145 0.05 0.125 0.04
11.76 0.20 0.50 0.10 0.68 0 - 5 0.13 0.05
1.20 Max
0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Mass (reference value)
TTP-44DE -- -- 0.43 g
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HM62W16255HC Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
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Hitachi Asia Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3rd Flr, Hung Kuo Building, No.167, Tun Hwa North Road, Taipei (105) Taiwan Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Telex: 23222 HAS-TP Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7th Flr, North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585160
Copyright (c) Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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